module enqueueUpdateDeMuxer32 (
    input wire clk,
    input wire rst,
    input wire enqueue_update_en_in,
    input wire [5:0] enqueue_update_priority_in,
    input wire [7:0] is_first_tail_in,
    input wire [15:0] enqueue_tail_old_in,
    input wire [15:0] enqueue_tail_new_in,
    output reg [31:0] enqueue_update_en_out,
    output reg [5:0] enqueue_update_priority_out [0:31],
    output reg [7:0] is_first_tail_out [0:31],
    output reg [9:0] enqueue_tail_old_out [0:31],
    output reg [15:0] enqueue_tail_new_out [0:31]
);

    integer i;

    always @(posedge clk) begin
        if (rst) begin
            //复位信号拉高时，将所有的使能信号拉低
            enqueue_update_en_out <= 32'h00000000;
            for (i=0; i<32; i=i+1) begin
                enqueue_update_priority_out[i] <= 0;
                is_first_tail_out[i] <= 0;
            end
        end
        else begin
            if (enqueue_update_en_in) begin
                enqueue_update_en_out <= (1 << enqueue_tail_old_in[15:10]);
                enqueue_update_priority_out[enqueue_tail_old_in[15:10]] <= enqueue_update_priority_in;
                is_first_tail_out[enqueue_tail_old_in[15:10]] <= is_first_tail_in;
                enqueue_tail_old_out[enqueue_tail_old_in[15:10]] <= enqueue_tail_old_in[9:0];
                enqueue_tail_new_out[enqueue_tail_old_in[15:10]] <= enqueue_tail_new_in;
            end
            else begin
                enqueue_update_en_out <= 32'h00000000;
            end
        end
    end
    
endmodule